Transistor level optimisation of digital cells

Integrated circuit manufacturers provide libraries of pre-designed digital cells for digital circuit design. The transistor level implementation of the cells is not considered during the design procedure. The cells, such as buffers, logic gates, adders, flip-flops, etc. are used without modifications wherever needed. For that reason the cells are not fine tuned to their unique surrounding conditions in the circuit. This leaves space for cell optimisation to be used as a tool for achieving arbitrary customisation. This paper describes a case study of transistor level digital cell optimisation. Since the landscape of the cost function used in the process of optimisation proved to be too noisy, the optimisation runs were performed using a robust global optimisation method. The results show that a substantial improvement of cell properties with respect to the manufacturer-supplied pre-designed cells can be obtained.